STEP 3: Getting started with Verilog
• Creating a new folder (better if you have all the files for a project in a
specific folder).
• Enter into this new folder and start writing your Verilog script in a
new file (.v file). Example code for modeling an counter is here
• In addition to model code, Test Bench script has to be given in order
to verify the functionality of your model (.v file). Example code of test
bench for counter is here.
Use gedit to edit the .v files
(gedit is a commonly used GUI editor on Linux )
Fig. 3 Open gedit through teminal
STEP 4: Compiling and simulating your code
• In the terminal, change the directory to where your model and test
bench files (Counter.v and Counter_tb.v) are present by using this
command:
cd <path>
For example:
cd ~/ESE461/VcsTutorial/
(Remark: ‘~’ means home directory on Linux)
• Compile the files by typing in the terminal:
vcs <file>.v <file_tb>.v
In the above example, it should be:
vcs Counter.v Counter_tb.v
There should be no error presented in the terminal. Otherwise you
need to check your code and correct them according to the related
message. The complier will print out detailed information about your
mistakes in the code.
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